1. Field of the Invention
The present invention relates to a method for producing a circuit board, for a semiconductor package, comprising a core substrate covered with metallic layers on the opposite surfaces thereof and having an opening for a cavity for accommodating a semiconductor element, wherein the cavity opening has a conductive layer on an inner wall thereof to be connected with a circuit pattern carried on one surface of the core substrate.
2. Description of the Related Art
A prior art method for producing a circuit board for a semiconductor package such as a plastic package or the like will be described with reference to FIGS. 4(a) to 4(i). An opening 54 for a cavity (herein after referred to as "a cavity opening") is formed by means of a drill (see FIG. 4(b)) in a copper-clad substrate 53 (see FIG. 4(a)) prepared by overlaying copper foils 52 on the opposite surfaces of a core substrate made of a glass cloth or others. Onto the inner wall of the cavity opening 54 of the copper-clad substrate 53 is applied an electroless plating of copper and then an electro-plating of copper to form a copper-plating film 55 on the opposite surfaces of the copper-clad substrate 53 as well as the inner wall of the cavity hole 54 (see FIG. 4(c)). In this regard, alternatively to the electroless plating of copper described above, after forming a palladium core on the inner wall of the cavity opening 54, an electroplating may be applied thereto.
Next, a photosensitive resist film 56 is formed on the opposite surfaces of the copper-clad substrate 53 (by, for example, a hot-press bonding of a dry film) (see FIG. 4(d)), and a photo-mask is overlaid with the resist layer 56, on which an exposure/development process is carried out. Thereby, a portion 56a of the photosensitive film 56 corresponding to a circuit pattern is hardened and left after a non-exposed portion 56b covered with the mask is dissolved (see FIG. 4(e)).
Thereafter, a tin-plating or solder-plating layer 57 is formed on a portion where the copper-plating film 55 is exposed on the copper-clad substrate 53 (corresponding to the circuit pattern) (see FIG. 4(f)). After the copper-plating film 55 exposed by peeling the photosensitive portion 56a of the photosensitive resist film 56 on the copper-clad substrate 53 and the copper foil 52 disposed beneath the same is removed by the etching (see FIG. 4(g)), the tin-plating or solder-plating layer 57 is removed by the dissolution, whereby a circuit pattern such as a signal line or a power source line covered with the copper-plating film 55 is formed on the opposite surfaces of the copper-clad substrate 53, and a conductive layer 55a to be connected with a circuit pattern such as a ground layer on the lower surface of the core substrate 51 is formed on the inner wall of the cavity opening 54 (see FIG. 4(h)).
After a semiconductor element 59 such as an LSI is accommodated in a cavity formed by bonding a heat-radiation plate 58 or the like on the lower surface of the copper-clad substrate 53, the signal lines or the power source lines formed on the upper surface of the copper-clad substrate 53 are connected with bonding pads of the semiconductor element 59 by a wire-bonding so that the semiconductor element is electrically connected to the circuit pattern via bonding wires 60 (see FIG. 4(i)).
In the cavity area, since the photo-mask overlaid with the photosensitive resist film 56 is formed along a profile of the periphery of the cavity opening 54, a deviation is liable to occur between the actual circuit pattern and the photo-mask.
Specifically, since the glass cloth used as the core substrate 51 is contractible or expandable due to heat, the core substrate 51 on which the dry film is bonded by a hot-press bonding is mobile prior to being subjected to the exposure/development process to deviate from the photo-mask. For example, as shown in FIG. 4(e), if the core substrate 51 expands, the portion 56a of the photosensitive resist film 56 may be displaced away from an upper periphery 54a of the cavity opening 54. When the conductive layer 55a is formed on the inner wall of the cavity opening 54, as shown in FIG. 4(c), for the purpose of the electrical conduction with the circuit pattern provided on the lower surface of the core substrate 51, the conductive layer 55a is formed even in an area wherein no conductive pattern is required, as shown in FIG. 4(h), if the photosensitive resist film 56 deviates from the upper periphery 54a.
Thereby, as shown in FIG. 4(i), when the wire-bonding is carried out after the semiconductor element 59 is accommodated in the cavity formed by bonding the heat radiation plate 58 with the lower surface of the copper-clad substrate 53, there is a risk in that the bonding wires 60 may be brought into contact with an edge 61 of the conductive layer 55a formed on the upper periphery 54a of the cavity opening 54. That is, since a bonding finger moves from the inside to the outside of the cavity opening 54 during the wire-bonding so that the bonding wire 60 streches from the bonding pad of the semiconductor element 59 within the cavity to that of the signal line or the power source line formed on the upper surface of the copper-clad substrate 53, there is a risk of the bonding wire 60 contacting the edge 61 of the conductive layer 55a formed on the upper periphery 54a, resulting in a short-circuit.